Stefanos Linakis
Development
SP, Brazil
Skills
Python
About
Stefanos H.'s skills align with Programmers (Information and Communication Technology). Stefanos also has skills associated with System Developers and Analysts (Information and Communication Technology). Stefanos H. has 11 years of work experience, with 2 years of management experience, including a mid-level position.
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Work Experience
PRINCIPAL VERIFICATION ENGINEER
RENESAS ELECTRONICS CORPORATION
March 2023 - December 2023
- Enhanced proficiency in Clocking Verification through the development of SystemVerilog Assertions for glitch detection and addressing critical clocking scenarios not readily identified by Legacy Verification Flow. • Acquired some expertise in leadership by leading a project until Tape-Out phase along with sharing knowledge and providing guidance to other project members. • Run/managed regressions by using vManager, delivering detailed reports and results to work team ahead of deadlines. • Created highly-acclaimed presentations that delved into most critical and relevant aspects of projects; received outstanding feedback from team members, direct manager and supervisors.
SYSTEM-ON-CHIP VERIFICATION TECHNICAL LEAD ENGINEER
HCL TECHNOLOGIES
August 2021 - February 2023
- Built-up know-how in SystemVerilog (SV) and Universal Verification Methodology (UVM) by building Testbench from scratch; enhanced current test environment to broaden verification scope. • Cultivated significant proficiency in scripting, leveraging Python and other languages to automate the generation of Testbench components. This initiative not only enhanced project efficiency but also enabled the team to consistently meet and surpass deadlines. • Gained expertise in Low-Power Verification and Universal Power Format (UPF) power-intent, validating power domains and powerrelated sub-systems in crucial and highly pertinent scenarios at SoC level.
SENIOR DESIGN VERIFICATION ENGINEER
QUALCOMM SEMICONDUCTORS
July 2019 - July 2021
- • Developed experience in Security and Cryptography for Core and Sub-System Verification. • Acquired considerable knowledge on Debug Architecture for Core and Sub-System Verification by driving more efficient effort. • Built crucial know-how on SystemVerilog and UVM along with Constrained Random Verification and SystemVerilog Assertion/Coverage. • Demonstrated great initiative and professional behaviour by supporting SoC Verification department and other high-demanding teams by fulfilling tight deadlines and exceeding initial expectations. • Received great acknowledgement for elaborating clever and highly acclaimed scripts to speed up verification, plunging effort in Core Verification, SoC Verification and System Validation/Emulation teams for several projects.
SYSTEM-ON-CHIP DIGITAL VERIFICATION ENGINEER
NXP SEMICONDUCTORS
July 2016 - June 2019
- Acquired considerable background on Clocking Architecture and Clock Domain Crossing verification by using an innovative verification approach to verify Clock-related Architecture; led to international and domestic publication. • Expanded expertise in MIPI Alliance specifications, placing a robust emphasis on System-on-Chip Graphic IPs Verification, mainly focused on GPUs and Display Controllers. • Elaborated software in Python for image-processing flow and Validation effort: images stored in memory were processed by software to predict actual GPU's output. A Graphical User Interface was also developed in Python to be more user-friendly and promote Validation team usage; received astonishing feedback from Director of Technology, leading the tool to be available for end client. • Developed knowledge on Low-Power related scenarios.
SYSTEM-ON-CHIP DIGITAL VERIFICATION ENGINEER
FREESCALE SEMICONDUCTORS
September 2014 - June 2016
- • Strongly engaged in the development of Micro-Controller & Micro-Processor projects with confidence and adherence to tight deadlines. • Extensively skilled in System-on-Chip Verification, with a particular focus on communication protocols and interconnections. • Ramped-up my knowledge in SystemVerilog and Universal Verification Methodology, resulting in the creation of noteworthy article. Received positive feedback from team members, supervisors, and the local Director of Operations. • Elaborated comprehensive and detailed verification plans allied with effective strategies for SoC verification; enhanced legacy Verification Intellectual Properties to verify critical SoC parts.
DEPARTMENT OFFICIAL PROGRAMMER INTERN
HUAWEI TECHNOLOGIES CORPORATION
August 2013 - July 2014
- • Devised and coded an efficient system by using C/C++/VBA languages, increasing Department data processing capacity by 150%. • Worked on hardware programming by using scripts in C/C++/HTML languages focused on protocols and the company software. • Managed high volume of clients among Brazilian and international cellular service providers; fulfilled several challenging Department deadlines focused on joint venture partners with national and international face to face meetings. • Trained at advanced courses related to Mobile Communications in association with the most renowned courses in Wireless access technologies (GSM - Global Standard Mobile; WCDMA - Wide-Band Code-Division Multiple Access; LTE - Long-Term Evolution).
ULTRA-HIGH SPEED OPTICAL COMMUNICATIONS DEPARTMENT INTERN
TELECOMMUNICATIONS RESEARCH AND DEVELOPMENT
August 2012 - July 2013
- Aug. 2012 - Jul. 2013 • Tailored a virtual platform in optical automation using LabVIEW, cooperating to develop the first Brazilian chip for Optical and Digital Signal Processing applications. • Engineered and published a new method capable of maximising the performance of high density metropolitan optical networks. • Worked on advanced optical simulators to analyze high density metropolitan networks. • Engaged in innovative ideas; published three national/international scientific articles directed at domestic & international Optics and Photonics conferences.
Education
UNIVERSIDADE ESTADUAL DE CAMPINAS
B.S. in Electrical Engineering
